The Encoder-6 I/O module is accessed using the IndustryPack® I/O space. Each channel’s count can be read with a 16 bit wide read access. A single read access resets all the channel counters. The overflow, index, and up/down registers can be read indicating the state of each channel. A write to the overflow and index register command clears the state of all channels. The interrupt vector can be programmed by writing the register bits d1 thru d7, (d0 is automatically determined by which of the two interrupts is active.) Each of the channels interrupts may be masked by setting the interrupt mask register; the overflow and index register will have the channel’s bit latched asserted but will not cause an interrupt to the host.

Programming

The Encoder-6 module will in general be programmed in the following manner:

1. At initialization the channels will be reset to zero by reading to offset 0x0C. Both the overflow and index registers should also be cleared. If a virtual counter of greater than 16 bits is desired, set up an interrupt service routine for INTRQ0 to increment or decrement the virtual counter upon receipt of the interrupt. If indexing is implemented, setup an interrupt service routine for INTRQ1 that saves the counter, or resets the counter upon receipt of the interrupt.

1.B (Rev B only) A vector can be set to respond to those carrier boards that implement the interrupt acknowledge, IntSel*, signal. A byte value should be placed on the low 8 bits of the IndustryPack® data bus using the I/O write access to the address specified in Table 1. The vector is presented on the bus when the IntSel* access is done with the value in the lowest bit, d0, indicating whether Int0 or Int1 is being requested; low for Int0 and high for Int1. For example, if the vector 0xaa is configured, then an acknowledgment of Int0 will yield the vector 0xaa, while an acknowledgment of Int1 will yield the vector 0xab.

1.C (Rev B only) The overflow and index capture mask registers should be set so that only channels required to interrupt the host have their bits unmasked.

2. To read a counter, do a word wide read of the desired channel.

3. If the virtual counter is implemented, the interrupt service routine upon receiving the interrupt, reads the overflow register to see which channel overflowed, reads the up/down register to see if it overflowed up or down, updates the virtual counter, and then clears the overflow register. Note that when reading the overflow register all channels should be checked as two or more channels may have overflowed at the same time.

. If the index capture input is implemented, the interrupt service routine upon receiving the interrupt, reads the index register to see which channel or channels had its index input asserted, records or initializes the corresponding counter, and then clears the index register.

Notes: – The overflow and index input capture signals are latched into their corresponding registers and thus the registers must be cleared in the interrupt service routine. – The HCTL-2020 counters multiply the resolution of the input signals by four.
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